Executive Summary

This vulnerability exists in the Chipsalliance Rocket-Chip's Control and Status Register (CSR) logic. It involves a flawed interaction between exception handling and the MRET (machine return) instruction. Specifically, when an exception is triggered during the execution of the MRET instruction, the exception handling and exception return mechanisms activate simultaneously, causing conflicting updates to the CSR. This can corrupt exception handling and privilege state transitions, leading to faulty trap behavior and potentially triggering an Instruction Access Fault when MRET is executed in machine mode outside of an exception state.

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Impact Analysis

The vulnerability can lead to corruption of exception handling and privilege state transitions in the affected system. This may cause unexpected or faulty trap behavior, potentially destabilizing the system or allowing attackers to interfere with the normal control flow and privilege levels. Such corruption could be exploited to bypass security mechanisms or cause denial of service by triggering faults during critical operations.

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