CVE-2025-56301
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Vulnerability report for CVE-2025-56301, including description, CVSS score, EPSS score, affected products, exploitability, helpful resources, and attack-flow context.

Publication date: 2025-09-30

Last updated on: 2025-10-17

Assigner: MITRE

Description

An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 (2025-01-29) allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an exception is triggered during MRET execution. The Control and Status Register (CSR) logic has a flawed interaction between exception handling and exception return (MRET) mechanisms which can cause faulty trap behavior. When the MRET instruction is executed in machine mode without being in an exception state, an Instruction Access Fault may be triggered. This results in both the exception handling logic and the exception return logic activating simultaneously, leading to conflicting updates to the control and status registers.

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Meta Information

Published
2025-09-30
Last Modified
2025-10-17
Generated
2026-07-06
AI Q&A
2025-09-30
EPSS Evaluated
2026-07-05
NVD

Affected Vendors & Products

Showing 1 associated CPE
Vendor Product Version / Range
chipsalliance rocket-chip 2025-01-29

Helpful Resources

Exploitability

CWE
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KEV
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CWE ID Description
CWE-1281 Specific combinations of processor instructions lead to undesirable behavior such as locking the processor until a hard reset performed.

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Executive Summary

This vulnerability exists in the Chipsalliance Rocket-Chip's Control and Status Register (CSR) logic. It involves a flawed interaction between exception handling and the MRET (machine return) instruction. Specifically, when an exception is triggered during the execution of the MRET instruction, the exception handling and exception return mechanisms activate simultaneously, causing conflicting updates to the CSR. This can corrupt exception handling and privilege state transitions, leading to faulty trap behavior and potentially triggering an Instruction Access Fault when MRET is executed in machine mode outside of an exception state.

Impact Analysis

The vulnerability can lead to corruption of exception handling and privilege state transitions in the affected system. This may cause unexpected or faulty trap behavior, potentially destabilizing the system or allowing attackers to interfere with the normal control flow and privilege levels. Such corruption could be exploited to bypass security mechanisms or cause denial of service by triggering faults during critical operations.

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