CVE-2023-54255
Unknown Unknown - Not Provided
DMA Channel Offset Calculation Flaw in Linux Kernel Causes Panics

Publication date: 2025-12-30

Last updated on: 2025-12-30

Assigner: kernel.org

Description
In the Linux kernel, the following vulnerability has been resolved: sh: dma: Fix DMA channel offset calculation Various SoCs of the SH3, SH4 and SH4A family, which use this driver, feature a differing number of DMA channels, which can be distributed between up to two DMAC modules. The existing implementation fails to correctly accommodate for all those variations, resulting in wrong channel offset calculations and leading to kernel panics. Rewrite dma_base_addr() in order to properly calculate channel offsets in a DMAC module. Fix dmaor_read_reg() and dmaor_write_reg(), so that the correct DMAC module base is selected for the DMAOR register.
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Meta Information
Published
2025-12-30
Last Modified
2025-12-30
Generated
2026-05-07
AI Q&A
2025-12-30
EPSS Evaluated
2026-05-05
NVD
EUVD
Affected Vendors & Products
Showing 1 associated CPE
Vendor Product Version / Range
linux linux_kernel *
Helpful Resources
Exploitability
CWE
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KEV
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CWE ID Description
CWE-UNKNOWN
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AI Powered Q&A
Can you explain this vulnerability to me?

This vulnerability is in the Linux kernel's DMA driver for certain SH3, SH4, and SH4A family SoCs. The driver incorrectly calculates DMA channel offsets because it does not properly handle the varying number of DMA channels distributed between up to two DMAC modules. This miscalculation can cause kernel panics due to wrong channel offset calculations. The fix involves rewriting the dma_base_addr() function to correctly calculate channel offsets and adjusting dmaor_read_reg() and dmaor_write_reg() to select the correct DMAC module base for the DMAOR register.


How can this vulnerability impact me? :

This vulnerability can cause kernel panics on affected systems, leading to system instability or crashes. Such crashes can disrupt normal operation, potentially causing data loss or service downtime on devices using the affected DMA driver on SH3, SH4, and SH4A SoCs.


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