CVE-2026-53354
Received Received - Intake

TLBI Errata Mitigation Required in Linux Kernel

Publication date: 2026-07-01

Last updated on: 2026-07-01

Assigner: kernel.org

Description
In the Linux kernel, the following vulnerability has been resolved: arm64: errata: Mitigate TLBI errata on various Arm CPUs A number of CPUs developed by Arm suffer from errata whereby a broadcast TLBI;DSB sequence may complete before the global observation of writes which are translated by an affected TLB entry. These errata ONLY affect the completion of memory accesses which have been translated by an invalidated TLB entry, and these errata DO NOT affect the actual invalidation of TLB entries. TLB entries are removed correctly. This issue has been assigned CVE ID CVE-2025-10263. To mitigate this issue, Arm recommends that software follows any affected TLBI;DSB sequence with an additional TLBI;DSB, which will ensure that all memory write effects affected by the first TLBI have been globally observed. The additional TLBI can use any operation that is broadcast to affected CPUs, and the additional DSB can use any option that is sufficient to complete the additional TLBI. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate the issue. Enable this workaround for affected CPUs, and update the silicon errata documentation accordingly. Note that due to the manner in which Arm develops IP and tracks errata, some CPUs share a common erratum number.

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Meta Information

Published
2026-07-01
Last Modified
2026-07-01
Generated
2026-07-01
AI Q&A
2026-07-01
EPSS Evaluated
N/A
NVD
CVE-2026-53354
EUVD
EUVD-2026-40988

Affected Vendors & Products

Showing 1 associated CPE
Vendor Product Version / Range
arm linux_kernel *

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CWE ID Description
CWE-UNKNOWN

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Executive Summary

This vulnerability affects certain Arm CPUs used in the Linux kernel. It involves an erratum where a broadcast TLBI;DSB sequence may complete before all memory writes translated by an invalidated TLB entry are globally observed. Although TLB entries are invalidated correctly, the timing issue can cause memory access completion to be observed prematurely.

To mitigate this, Arm recommends following any affected TLBI;DSB sequence with an additional TLBI;DSB operation to ensure all memory write effects are globally observed. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to address this issue.

Impact Analysis

This vulnerability can impact system stability and correctness by causing memory accesses to appear completed before all related memory writes are globally observed. This could potentially lead to unexpected behavior in software relying on memory consistency, especially in multi-core or multi-processor environments using affected Arm CPUs.

Mitigation Strategies

To mitigate this vulnerability, enable the ARM64_WORKAROUND_REPEAT_TLBI workaround on affected CPUs.

This workaround involves following any affected TLBI;DSB sequence with an additional TLBI;DSB to ensure all memory write effects are globally observed.

Additionally, update the silicon errata documentation accordingly to reflect this mitigation.

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