RTL and Netlist Mismatch in OpenRISC OR1200

Publication date: 2026-08-26

Last updated on: 2026-09-09

Assigner: MITRE

Description

An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior.

CVSS Scores

EPSS Scores

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Meta Information

Published

2026-08-26

Last Modified

2026-09-09

Generated

2026-09-16

AI Q&A

2026-08-27

EPSS Evaluated

2026-09-15

NVD

CVE-2025-51679

Affected Vendors & Products

Vendor	Product	Version / Range
openrisc	or1200	*

Helpful Resources

Exploitability

CWE

KEV

CWE ID	Description
CWE-1281	Specific combinations of processor instructions lead to undesirable behavior such as locking the processor until a hard reset performed.

Attack-Flow Graph

Executive Summary

This vulnerability involves a mismatch between the RTL (Register Transfer Level) design and the netlist in the openRISC OR1200 processor. This discrepancy can cause unexpected behavior in the hardware, potentially leading to system malfunctions or security issues.

Impact Analysis

The impact depends on how the OR1200 processor is used. If it is part of critical systems like embedded devices or IoT, unexpected behavior could lead to system failures, data corruption, or security breaches. However, specific impacts are not detailed in the provided context.

Mitigation Strategies

Update the openRISC OR1200 RTL and netlist to ensure consistency. Review hardware designs for mismatches between RTL and netlist implementations.

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