CVE-2026-12629
Received Received - Intake

Interrupt Storm in ARM PL011 UART Driver

Vulnerability report for CVE-2026-12629, including description, CVSS score, EPSS score, affected products, exploitability, helpful resources, and attack-flow context.

Publication date: 2026-08-17

Last updated on: 2026-08-17

Assigner: Zephyr Project

Description

The ARM PL011 UART driver in drivers/serial/uart_pl011.c fails to acknowledge receive error interrupts. On the PL011, the framing, parity, break, and overrun error interrupts (PL011_IMSC_ERROR_MASK) are cleared only by writing the interrupt-clear register UARTICR; reading the data register clears the RX interrupt and the per-byte RSR status but not the error interrupt status in MIS. The interrupt service routine pl011_isr() acknowledged only the CTS modem-status interrupt and never wrote icr for the error bits, so an asserted error interrupt remains pending after the ISR returns. When an application enables error-interrupt reporting via the public uart_irq_err_enable() API, an attacker who controls the serial peer can deterministically assert these error bits by injecting line errors on the RX line β€” a baud/stop-bit mismatch or mid-character break (framing/break error), a flipped parity bit (parity error), or FIFO flooding (overrun error). Because the error interrupt is never cleared, the interrupt line stays asserted and the CPU re-enters pl011_isr() immediately and indefinitely, producing an interrupt-storm livelock from which the core makes no forward progress. The impact is an availability-only denial of service (permanent hang), reachable from an external or removable UART peer. Exploitation is gated by configuration: the error interrupt is off by default and no in-tree subsystem enables it, so only applications that explicitly call uart_irq_err_enable() on a PL011-based, interrupt-driven port are affected. The fix makes pl011_isr() acknowledge the pending error bits via uart->icr, breaking the loop, and additionally clears the latched RSR status in pl011_err_check().

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Meta Information

Published
2026-08-17
Last Modified
2026-08-17
Generated
2026-08-17
AI Q&A
2026-08-17
EPSS Evaluated
N/A
NVD
EUVD

Affected Vendors & Products

Showing 1 associated CPE
Vendor Product Version / Range
zephyrproject zephyr From 1.14.0 (inc) to 4.4.2 (exc)

Helpful Resources

Exploitability

CWE
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KEV
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CWE ID Description
CWE-835 The product contains an iteration or loop with an exit condition that cannot be reached, i.e., an infinite loop.

Attack-Flow Graph

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Executive Summary

The vulnerability involves the ARM PL011 UART driver failing to clear receive error interrupts. Error interrupts like framing, parity, break, and overrun errors are only cleared by writing to the interrupt-clear register (UARTICR). The interrupt service routine does not handle these errors, leaving them pending. An attacker can trigger an infinite loop of interrupts by injecting line errors, causing a denial of service.

Detection Guidance

To detect this vulnerability, check if your system uses the ARM PL011 UART driver in Zephyr RTOS versions between 1.14.0 and 4.4.1. Verify if the uart_irq_err_enable API is enabled on any PL011-based interrupt-driven port. Monitor for continuous CPU interrupts or system hangs that may indicate an interrupt storm.

Impact Analysis

This vulnerability can cause a permanent system hang or denial of service. It requires the error interrupt to be explicitly enabled via uart_irq_err_enable(), which is off by default. Only systems using PL011-based UART with enabled error interrupts are affected. Exploitation is possible from an external UART peer.

Mitigation Strategies

Upgrade Zephyr RTOS to version 4.4.2 or later to apply the fix. If upgrading is not possible, disable the uart_irq_err_enable API on affected PL011 ports. Ensure the interrupt service routine clears error interrupts via UARTICR and clears RSR status after reading.

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