CVE-2026-74276
Received Received - Intake

Buffer Overflow in Linux Kernel SPI Xilinx Driver

Vulnerability report for CVE-2026-74276, including description, CVSS score, EPSS score, affected products, exploitability, helpful resources, and attack-flow context.

Publication date: 2026-08-15

Last updated on: 2026-08-15

Assigner: kernel.org

Description

In the Linux kernel, the following vulnerability has been resolved: spi: xilinx: use FIFO occupancy register to determine buffer size The method the driver uses to determine the size of the FIFO has a problem. What it currently does is this: It stops the SPI hardware and writes to the TX FIFO register until TX FIFO FULL asserts in the status register. But the hardware does not only have the FIFO, it also has a shift register which can hold a byte. This can be seen, when writing a byte to the FIFO (while the SPI hardware is stopped,) the TX FIFO EMPTY is still empty. So, if we have a FIFO size of 16 for example, the current method returns a 17. This is a problem, at least when using the driver in irq mode. The same size determined for the TX FIFO is also assumed for the RX FIFO. When a SPI transaction wants to write the amount of the FIFO size or more bytes, the following happens, for example with 16 bytes FIFO size: The driver stops the SPI hardware and writes 17 bytes to the TX FIFO and starts the SPI hardware and goes sleep. The hardware then shifts out 17 bytes (FIFO + shift register) and simultaneously reads bytes into the RX FIFO, but it only has 16 places, so it looses one byte. Then TX FIFO empty asserts, wakes the driver again, which has a fast path and reads 16 bytes from the RX FIFO, but before reading the last 17th byte (which is lost) it does this: sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); if (!(sr & XSPI_SR_RX_EMPTY_MASK)) { xilinx_spi_rx(xspi); rx_words--; } It reads the status register and checks if the RX FIFO is not empty. But it is empty in our case. So this check spins in a while loop forever locking the driver. This patch fixes the logic to determine the FIFO size.

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Meta Information

Published
2026-08-15
Last Modified
2026-08-15
Generated
2026-08-15
AI Q&A
2026-08-15
EPSS Evaluated
N/A
NVD
EUVD

Affected Vendors & Products

Showing 1 associated CPE
Vendor Product Version / Range
xilinx linux_kernel *

Helpful Resources

Exploitability

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CWE ID Description
CWE-UNKNOWN

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Executive Summary

This vulnerability in the Linux kernel's Xilinx SPI driver involves incorrect FIFO size detection. The driver mistakenly includes an extra byte from the shift register when measuring the TX FIFO size, leading to a reported size one byte larger than actual. This causes data loss during SPI transactions, as the RX FIFO overflows while the driver waits indefinitely for a non-empty status.

Detection Guidance

This vulnerability is specific to the Linux kernel's Xilinx SPI driver and requires kernel-level inspection. Detection involves checking the kernel version and SPI driver behavior. Use commands like 'uname -a' to verify kernel version and 'dmesg | grep spi' to inspect SPI driver logs for errors or unusual behavior.

Impact Analysis

If you use the affected Xilinx SPI driver in interrupt mode, this flaw can cause system hangs or crashes during SPI data transfers. Data corruption may occur due to RX FIFO overflow, and the driver may become unresponsive, requiring a reboot to recover.

Mitigation Strategies

Apply the kernel patch that fixes the FIFO size determination logic. Update to a patched kernel version if available. If using a custom kernel, backport the fix from the upstream Linux kernel. Monitor SPI driver behavior after applying changes.

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