CVE-2026-73450
Received Received - Intake

Arista EOS MLAG Dual Primary Detection Packet Interference Vulnerability

Publication date: 2026-09-16

Last updated on: 2026-09-16

Assigner: Arista Networks, Inc.

Description
On affected platforms running Arista EOS with MLAG Dual Primary Detection configured, an unauthenticated attacker with access to the Dual Primary Detection network segment can send specially crafted packets to interfere with the dual-primary state. If the MLAG primary switch fails while these packets are present, the secondary switch incorrectly concludes it is in a dual-primary condition and err-disables its interfaces, leading to a traffic interruption.

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Meta Information

Published
2026-09-16
Last Modified
2026-09-16
Generated
2026-10-06
AI Q&A
2026-09-16
EPSS Evaluated
2026-10-05
NVD
CVE-2026-73450
EUVD
EUVD-2026-80083

Affected Vendors & Products

Showing 1 associated CPE
Vendor Product Version / Range
arista arista_eos *

Helpful Resources

Exploitability

CWE
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KEV
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CWE ID Description
CWE-345 The product does not sufficiently verify the origin or authenticity of data, in a way that causes it to accept invalid data.

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Executive Summary

This vulnerability affects Arista EOS devices with MLAG Dual Primary Detection enabled. An unauthenticated attacker on the Dual Primary Detection network segment can send crafted packets to disrupt the dual-primary state. If the primary switch fails while these packets are present, the secondary switch may incorrectly detect a dual-primary condition and disable its interfaces, causing network traffic interruption.

Impact Analysis

The impact includes network downtime due to interface err-disabling on the secondary MLAG switch. This can lead to loss of connectivity and service disruption for users and systems relying on the affected network segment.

Mitigation Strategies

Disable MLAG Dual Primary Detection on affected Arista EOS devices or restrict access to the Dual Primary Detection network segment to prevent unauthorized packet injection. Monitor logs for err-disabled interfaces and ensure secondary switches do not incorrectly trigger dual-primary conditions.

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